[llvm-dev] accessing subwords in memory

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[llvm-dev] accessing subwords in memory

Robin Eklind via llvm-dev
I'm targeting a machine that can only load and store aligned 64-bit words,
but I'd like to be able to pack 8-, 16-, and 32-bit values into these words.
Loads will require various shifts and masks; stores are more complicated.
Does LLVM provide any support for such things?
Is there an example target I can look at for ideas?

Thanks,
Preston


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Re: [llvm-dev] accessing subwords in memory

Robin Eklind via llvm-dev
On 06/26/2018 12:06 PM, Preston Briggs via llvm-dev wrote:
> I'm targeting a machine that can only load and store aligned 64-bit words,
> but I'd like to be able to pack 8-, 16-, and 32-bit values into these words.
> Loads will require various shifts and masks; stores are more complicated.
> Does LLVM provide any support for such things?
> Is there an example target I can look at for ideas?
>

The R600 subtarget in the AMDGPU backend does this with loads/stores for some
address spaces.  See R600TargetLowering::lowerPrivateExtLoad()
and R600TargetLowering::lowerPrivateTruncStore().

-Tom

> Thanks,
> Preston
>
>
>
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> LLVM Developers mailing list
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Re: [llvm-dev] accessing subwords in memory

Robin Eklind via llvm-dev
In reply to this post by Robin Eklind via llvm-dev

> I'm targeting a machine that can only load and store aligned 64-bit words,

Does this imply that the target uses word addresses instead of byte addresses?

Boris

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Re: [llvm-dev] accessing subwords in memory

Robin Eklind via llvm-dev
On Wed, Jun 27, 2018 at 12:32 AM, Boris Boesler <[hidden email]> wrote:
> > I'm targeting a machine that can only load and store aligned 64-bit words,
>
> Does this imply that the target uses word addresses instead of byte addresses?

The machine uses byte addresses, but lacks instructions to do things like load/store byte.
So we must load a word, then find the desired byte.

Preston


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