[llvm-dev] Vectorization in LLVM x86 backend

Previous Topic Next Topic
 
classic Classic list List threaded Threaded
2 messages Options
Reply | Threaded
Open this post in threaded view
|

[llvm-dev] Vectorization in LLVM x86 backend

Matthias Braun via llvm-dev
Hi all,

Recently I compiled the attached .c file using Clang with "-mavx2 -mfma -m32 -O3" optimization flags. 

First I used -emit-llvm and inspected the LLVM IR (.ll file attached) and there are no vector instructions in the if.else BB in compressStream function. Then I got the assembly output of the file in it I can clearly see vector instructions in the compressStream function (.S file attached)

Neither the SLPVectorizer or the LoopVectorizer is however doing any vectorization (also checked it using -debug-only flag) as witnessed by the non-vectorized code in the attached .ll file. 

Therefore, the vectorization should happen in the backend(?). 

Can I know whether the x86 backend does additional vectorization of scalar code and if so in which passes?

Thank You.

--
Kind regards,
Charith Mendis

Graduate Student,
CSAIL,
Massachusetts Institute of Technology

_______________________________________________
LLVM Developers mailing list
[hidden email]
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

bzip2.c (84K) Download Attachment
bzip2.ll (118K) Download Attachment
bzip2.s (58K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

Re: [llvm-dev] Vectorization in LLVM x86 backend

Matthias Braun via llvm-dev
I will qualify this answer with a caveat that I know nothing about X86.
I presume that the vector instructions in the assembly that you're referring to are things like vaddsd, vmulsd, vdivsd, ... (simply because I assume the v stands for vector).

If that is the case, you should note that those are not vector instructions as far as the SDAG is concerned. If you compile this IR file with -debug-only=isel, you'll notice where these are coming from. Namely, there will be nodes such as t99: f64 = VADDSDrr t98, t300. Notice - it is not a vector result. These come from nodes such as t99: f64 = fadd t98, t300 via patterns such as:
// Src: (fadd:f64 FR64:f64:$src1, FR64:f64:$src2) - Complexity = 3
// Dst: (VADDSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)


If these are not the instructions you're referring to, then either they come from similar patterns or this response does not apply. But one thing that seems quite certain is that the basic block does not contain any vectors according to the SDAG (i.e. there are no vXXfYY types in the SDAG).

On Mon, Aug 21, 2017 at 9:09 AM, Charith Mendis via llvm-dev <[hidden email]> wrote:
Hi all,

Recently I compiled the attached .c file using Clang with "-mavx2 -mfma -m32 -O3" optimization flags. 

First I used -emit-llvm and inspected the LLVM IR (.ll file attached) and there are no vector instructions in the if.else BB in compressStream function. Then I got the assembly output of the file in it I can clearly see vector instructions in the compressStream function (.S file attached)

Neither the SLPVectorizer or the LoopVectorizer is however doing any vectorization (also checked it using -debug-only flag) as witnessed by the non-vectorized code in the attached .ll file. 

Therefore, the vectorization should happen in the backend(?). 

Can I know whether the x86 backend does additional vectorization of scalar code and if so in which passes?

Thank You.

--
Kind regards,
Charith Mendis

Graduate Student,
CSAIL,
Massachusetts Institute of Technology

_______________________________________________
LLVM Developers mailing list
[hidden email]
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev



_______________________________________________
LLVM Developers mailing list
[hidden email]
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev