[llvm-dev] Target hardware loop instruction via intrinsics

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[llvm-dev] Target hardware loop instruction via intrinsics

Bruce Hoult via llvm-dev
Hi,

Hexagon has a MIR pass for detecting loops that map onto hardware support. I think a similar approach would be viable for my target but am put off by the complexity of determining whether a given loop is legal to transform.

Instead, I would like to pass the responsibility for determining legality onto the C programmer who is assumed sufficiently familiar with the architecture.

I think this would require a pair of intrinsics to denote the start and end of the loop. Is there a reasonable way to model this in llvm?

If not, would anyone suggest a compiler programmer friendly, even if application programmer hostile, way to target a loop instruction with many constraints on validity.

Thanks!

Jon

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Re: [llvm-dev] Target hardware loop instruction via intrinsics

Bruce Hoult via llvm-dev

On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev wrote:
Hi,

Hexagon has a MIR pass for detecting loops that map onto hardware support. I think a similar approach would be viable for my target but am put off by the complexity of determining whether a given loop is legal to transform.

I think that it is easier to do this legality checking at the IR level (where we can take advantage of the ScalarEvolution analysis). This is what PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend that you take this approach if possible.

 -Hal


Instead, I would like to pass the responsibility for determining legality onto the C programmer who is assumed sufficiently familiar with the architecture.

I think this would require a pair of intrinsics to denote the start and end of the loop. Is there a reasonable way to model this in llvm?

If not, would anyone suggest a compiler programmer friendly, even if application programmer hostile, way to target a loop instruction with many constraints on validity.

Thanks!

Jon


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-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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Re: [llvm-dev] Target hardware loop instruction via intrinsics

Bruce Hoult via llvm-dev
That's a good idea, thanks!

On Thu, Jun 21, 2018 at 7:25 PM, Hal Finkel <[hidden email]> wrote:

On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev wrote:
Hi,

Hexagon has a MIR pass for detecting loops that map onto hardware support. I think a similar approach would be viable for my target but am put off by the complexity of determining whether a given loop is legal to transform.

I think that it is easier to do this legality checking at the IR level (where we can take advantage of the ScalarEvolution analysis). This is what PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend that you take this approach if possible.

 -Hal

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Re: [llvm-dev] Target hardware loop instruction via intrinsics

Bruce Hoult via llvm-dev
In reply to this post by Bruce Hoult via llvm-dev
Hi Jon,

On Thu, 21 Jun 2018 at 19:08, Jon Chesterfield via llvm-dev
<[hidden email]> wrote:
> I think this would require a pair of intrinsics to denote the start and end of the loop. Is there a reasonable way to model this in llvm?

Have you looked into how OpenMP vectorization pragmas are handled yet?
I only glanced at it out of curiosity the other week but it looks like
they attach some "!loop" metadata to the back-edge branch of the loop
involved. It looks string-based and so reasonably extensible, and
legality is already one of the bits of information encoded.

What I don't know is whether that's available to MIR if you end up
doing your work there. The main vectorizers act on IR.

Cheers.

Tim.
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