[llvm-dev] Store Instruction pattern match

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[llvm-dev] Store Instruction pattern match

Bruce Hoult via llvm-dev

Hi, I am trying to develop new llvm backend based on RISCV architecture for practice.

using --debug option on llc tool, I got this error message.  

 

LLVM ERROR: Cannot select: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32

 

So I have questions on this problem.

1. Does this mean there is no SDNode matching the store pattern like that?  

 

2.  In LLVM language reference, the 'store' command pattern looks like this

store [volatile] <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>][, !invariant.group !<index>]   

Based on this pattern, I define the store instruction in my *InstrInfo.td like this

def STORE : MemStore_RISCVS<0b0100011, 0b010, "st", st, simm12, immSExt12, VR6Regs>; 

because In RISCV, store instruction has 2 registers and 12 bit immediate value.  

Bit in the log upside there, it seems the word 'undef' makes the problem. ( This is just my assumption, so it could be wrong. If i am wrong, please correct me)

Should I change my InstrInfo.td file then...?  


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Re: [llvm-dev] Store Instruction pattern match

Bruce Hoult via llvm-dev


On Jun 18, 2018, at 05:06, ComputerFreak via llvm-dev <[hidden email]> wrote:

Hi, I am trying to develop new llvm backend based on RISCV architecture for practice.
using --debug option on llc tool, I got this error message.  

 

LLVM ERROR: Cannot select: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32

 

So I have questions on this problem.
1. Does this mean there is no SDNode matching the store pattern like that?  

 

2.  In LLVM language reference, the 'store' command pattern looks like this
store [volatile] <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>][, !invariant.group !<index>]   

Based on this pattern, I define the store instruction in my *InstrInfo.td like this
def STORE : MemStore_RISCVS<0b0100011, 0b010, "st", st, simm12, immSExt12, VR6Regs>; 
because In RISCV, store instruction has 2 registers and 12 bit immediate value.  
Bit in the log upside there, it seems the word 'undef' makes the problem. ( This is just my assumption, so it could be wrong. If i am wrong, please correct me)
Should I change my InstrInfo.td file then...?  
<llc.log>______________________________________________


You aren’t directly matching against the IR store instruction, you are matching against the store ISD node, which is slightly different.
The undef is probably OK since that’s the addressing mode offset for the load, which only some targets use.

I believe it isn’t generally recommend to try to match “st” directly, and match the more constrained store PatFrags (e.g. store and all the various type truncstores)

-Matt


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