[llvm-dev] Sparc CASA instruction encoding

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[llvm-dev] Sparc CASA instruction encoding

Alex Brachet-Mialot via llvm-dev
Hi,

I have tried to add the LEON CASArr instruction as part of a Sparc Subtarget to the Sparc instructions. Almost all the tests I've written have worked without problem, but when I try to encode the instruction, it doesn't work.

I modelled it on the CASrr instruction which it basically mimics in every regard except the ASI.

// The CAS instruction, unlike other instructions, only comes in a 
// form which requires an ASI be provided. The ASI value hardcoded 
// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
  def CASrr: F3_1_asi<3, 0b111100,
                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                     IntRegs:$swap),
                 "cas [$rs1], $rs2, $rd",
                 [(set i32:$rd,
                     (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))], 
                 NoItinerary>;


// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
// CASrr, above, but with a different ASI.
// Requires the use of SparcV8's default ASI, 0xA ("User Data").
let Predicates = [CASASupported], Constraints = "$swap = $rd", asi = 0b00001010 in
  def CASArr: F3_1_asi<3, 0b111100,
                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                     IntRegs:$swap),
                 "casa [$rs1], $rs2, $rd",
                 [(set i32:$rd,
                     (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))], 
                 NoItinerary>;

However, when I get the following trying to encode the instruction to binary:

$ llvm-mc leon-atomic-instructions.s -arch=sparc -mcpu=gr712rc -show-encoding
.text
leon-atomic-instructions.s:4:15: error: invalid operand for instruction
        casa [%i0], %l6, %o2

The only operative line in leon-atomic-instructions is the one that throws the error. gr712rc is the name of the CPU I've added, which switches on the "CASASupported" feature that you can see in the instruction definition above. All this part of the system works, so it's almost certainly nothing there - plus I've performed many tests to verify this.

I've also run the pre-existing test in test/MC/Sparc: llvm-mc sparcv9-atomic-instructions -arch=sparc -show-encoding. This works fine and I don't get any such error ("invalid operand for instruction") on "cas [%i0], %l6, %o2".

Can anyone explain why I get a difference between the two and what I need to change?

Best Regards,
Chris Dewhurst.
University of Limerick.

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Re: [llvm-dev] Sparc CASA instruction encoding

Alex Brachet-Mialot via llvm-dev
Hi Chris,

On 16 November 2015 at 03:36, Chris.Dewhurst via llvm-dev
<[hidden email]> wrote:
> Can anyone explain why I get a difference between the two and what I need to
> change?

It looks like Sparc has a special hack for "cas" and "casx" in
AsmParser/SparcAsmParser.cpp (top of the parseOperand function). You
probably need to add "casa" to the list of mnemonics checked.

Cheers.

Tim.
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