[llvm-dev] [SelectionDAG] lowering shifts to parts

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[llvm-dev] [SelectionDAG] lowering shifts to parts

Muhui Jiang via llvm-dev

This is what I hope is a simple question about target lowering. The target has 64 bit registers and support for some but not all 64-bit operations. It does not support 64-bit shifts. What I would like to do is have them lowered to SHL_PARTS.

 

In target lowering I set i64 as a legal type, since most operations are supported and we have 64 bit registers. This has the unfortunate effect of preventing type legalization from lowering the shifts to SHL_PARTS.

 

So I tried setOperationAction(ISD::SHL, MVT::i64, Expand), but then I get an assertion failure because apparently the expander cannot handle scalar shifts.

 

Is there some other way? Do I need to make a custom action? If so, can I just call ExpandIntRes_Shift(), which performs that transformation for type legalization?

 

More generally, is there another target that does something similar? What’s the preferred approach for handling partial support for a given type?

 

-Alan


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Re: [llvm-dev] [SelectionDAG] lowering shifts to parts

Muhui Jiang via llvm-dev
On 6/29/2018 8:18 AM, Davis, Alan via llvm-dev wrote:
>
> Is there some other way? Do I need to make a custom action? If so, can I
> just call ExpandIntRes_Shift(), which performs that transformation for
> type legalization?

Yes, you need to implement custom lowering to the operations that are
legal on your target. You cannot call ExpandResInt_Shift because that
function is not available in target lowering (it's a function in the
type legalizer). Your lowering to parts will need to combine the results
into a value of type i64, so that the result type will match the
original type of the shift.

-Krzysztof

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