[llvm-dev] Selecting different instructions depending on addrspace() value

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[llvm-dev] Selecting different instructions depending on addrspace() value

Sudhindra kulkarni via llvm-dev
Hello.

In my backend I have pointers in different address spaces. I want to emit different instructions based on addrspace value, but I can't find a way to do that.

It seems not possible to do that with usual "store" pattern fragment in .td file, so I added custom ISD opcode for my instruction and created it manually in MyBackendISelLowering. However, it doesn't get selected now, no matter what I try.

The code I currently have in InstrInfo.td:

def my_store         : SDNode<"MYISD::STORE"      , SDTStore,
                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;

let mayStore = 1 in {
def MyStore : InstMyRI<2, (outs), (ins i32imm:$i, IntRegs:$reg),
                     "", [(my_store i32:$reg, imm:$i)]>;
}

The error I get:

ISEL: Starting selection on root node: t15: ch = <<Unknown Target Node #278>> t13:1, Constant:i32<5>, FrameIndex:i32<-3>
ISEL: Starting pattern match
  Initial Opcode index to 4
  Match failed at index 10
LLVM ERROR: Cannot select: t15: ch = <<Unknown Target Node #278>> t13:1, Constant:i32<5>, FrameIndex:i32<-3>
  t2: i32 = Constant<5>
  t14: i32 = FrameIndex<-3>


Thanks in advance for your help.

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Re: [llvm-dev] Selecting different instructions depending on addrspace() value

Sudhindra kulkarni via llvm-dev
Hi Gleb,

On Thu, 21 Mar 2019 at 12:36, Gleb Popov via llvm-dev
<[hidden email]> wrote:
> It seems not possible to do that with usual "store" pattern fragment in .td file,

I think it ought to be possible without a custom ISD node. The AMDGPU
backend has a very similar situation and it looks like it has resolved
the problem by instantiating CodePatPred to check
cast<MemSDNode>(N)->getAddressSpace() as part of its patterns.

> The error I get:
>
> ISEL: Starting selection on root node: t15: ch = <<Unknown Target Node #278>> t13:1, Constant:i32<5>, FrameIndex:i32<-3>
> ISEL: Starting pattern match
>   Initial Opcode index to 4
>   Match failed at index 10

The best way to resolve these issues is to look at the table it's
referencing, in build/lib/Target/XYZ/XYZGenDAGISel.inc. The index
numbers mentioned in the error message appear as part of the comments
on each line, and you can usually use trace in the error work out
which pattern you expected to match and which predicate unexpectedly
failed.

My best guess from your post would be that the order of the pointer
and value operands appear to be swapped compared to a normal store. It
could still be right, depending on the contents of XYZISelLowering,
but is a little odd.

Cheers.

Tim.
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