[llvm-dev] Putting "tied-to" constraints on virtual registers in SelectionDAGISel's Select() method

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[llvm-dev] Putting "tied-to" constraints on virtual registers in SelectionDAGISel's Select() method

Gerion Entrup via llvm-dev
   Hello.
     I expand an instruction to a sequence of MachineSDNodes at instruction selection, in
the Select() method of the SelectionDAGISel class.
     For efficiency, in order to generate fewer instructions, I would like to assign twice
to the same physical register - but since I don't want to "mess" with the register
allocator, I am using only virtual registers.
     However, if I write in my C++ code 2 getCopyToReg() calls to the same virtual
register - this gives me the following error: "getVRegDef assumes a single definition or
no definition" later, after instruction selection.
     Therefore, I try to use 2 virtual registers for the same physical register. I know in
TablGen instruction specs we can give "tied-to" constraints on virtual registers of the form:
       string Constraints = "$regInput = $regOutput";

     Can we put such "tied-to" constraints programatically also at instruction selection,
in the Select() method of the SelectionDAGISel class?

   Thank you,
     Alex
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Re: [llvm-dev] Putting "tied-to" constraints on virtual registers in SelectionDAGISel's Select() method

Gerion Entrup via llvm-dev
On 6/6/2017 9:40 AM, Alex Susu via llvm-dev wrote:

>   Hello.
>     I expand an instruction to a sequence of MachineSDNodes at
> instruction selection, in the Select() method of the SelectionDAGISel
> class.
>     For efficiency, in order to generate fewer instructions, I would
> like to assign twice to the same physical register - but since I don't
> want to "mess" with the register allocator, I am using only virtual
> registers.
>     However, if I write in my C++ code 2 getCopyToReg() calls to the
> same virtual register - this gives me the following error: "getVRegDef
> assumes a single definition or no definition" later, after instruction
> selection.
>     Therefore, I try to use 2 virtual registers for the same physical
> register. I know in TablGen instruction specs we can give "tied-to"
> constraints on virtual registers of the form:
>       string Constraints = "$regInput = $regOutput";
>
>     Can we put such "tied-to" constraints programatically also at
> instruction selection, in the Select() method of the SelectionDAGISel
> class?
>

You have to specify "Constraints" in TableGen: it's a property of the
instruction.  That said, because it's a property of the instruction, it
still applies to nodes selected using C++ code in Select().

-Eli

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Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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