[llvm-dev] LLVM Weekly - #233, June 18th 2018

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[llvm-dev] LLVM Weekly - #233, June 18th 2018

Jeremy Lakeman via llvm-dev
LLVM Weekly - #233, June 18th 2018

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Welcome to the two hundred and thirty-third issue of LLVM Weekly, a weekly
newsletter (published every Monday) covering developments in LLVM, Clang, and
related projects. LLVM Weekly is brought to you by [Alex
Bradbury](https://www.linkedin.com/in/alex-bradbury/). Subscribe to future
issues at <http://llvmweekly.org> and pass it on to anyone else you think may
be interested. Please send any tips or feedback to <[hidden email]>, or
@llvmweekly or @asbradbury on Twitter.

## News and articles from around the web

The 2018 LLVM Developers' Meeting has been
for October 17th-18th in San Jose. Registration is [now

zapcc, a caching C++ compiler based on Clang is now [open
source](https://github.com/yrnkrn/zapcc). It claims substantial speedups for
heavily-templated C++. See this [previous cfe-dev
post](http://lists.llvm.org/pipermail/cfe-dev/2015-May/043155.html) for an
overview of the technology.

## On the mailing lists

* Hal Finkel is
[arranging](http://lists.llvm.org/pipermail/cfe-dev/2018-June/058229.html) a
[poll](https://doodle.com/poll/4qstmakgw3fykuf4) on the date to hold a webinar
on the proposed rewrite of Flang, "Clang for Fortran".

* Alex Bradbury kicked off an RFC thread on the [lowering of atomic LL/SC loop
in LLVM](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html). This
revisits a topic
[raised](http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) by
James Knight in 2016. Most architectures have restrictions on the form of an
LL/SC loop (e.g. number and type of instructions, presence of other memory
accesses) in order to guarantee forward progress. This thread proposes a late
expansion lowering strategy for the inner LL/SC loop, while expanding anything
else at the IR level. Tim Northover is
about possible performance loss, and Krzysztof Parzyszek
that Hexagon actually has no real restrictions on LL/SC loops.

* Pavel Labath has given an
[update](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123986.html) on
efforts to add DWARF5 accelerator table support to LLVM, while Paul Robinson
gave a broad update on [DWARF v5

* Paul Robinson started a discussion on [bug-closing

## LLVM commits

* A new compact binary format is supported for sample profiles, reducing the
size by about 2/3rds. [r334447](https://reviews.llvm.org/rL334447).

* Codegen support for atomics has started to land for RISC-V.

* The microMIPS size reduction pass has been extended to transform SW/LW pairs
to SWP/LWP. [r334595](https://reviews.llvm.org/rL334595).

* There is now a default SelectionDAG expansion for rotates.

* A new merge-git.sh script has been added, performing similar functionality
to the svn-based merge.sh script.

## Clang commits

* The new `-fforce-emit-vtables` option forces the emission of vtables even in
modules where it isn't necessary, which increases opportunities for
devirtualisation. [r334600](https://reviews.llvm.org/rL334600).

* clang-format gained a new BreakInheritanceList option.

## Other project commits

* Initial Hexagon support was committed to LLD.

* XRay Profiling Mode can now write profiles to files. Future work will enable
support for loading, converting, and analysing them with the llvm-xray tool.
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