Ive started writing a backend to a simple 32bit RISC processor core with
the goal of undertaking some flexible instruction processor core research
on FPGAs and also to use it for teaching computer architecture.
I have a requirement to generate instructions like below, where the (17bit)
immediate value is (preferably) omitted if it has a zero value.
add %15, %14
add %12, %23 - 18
mov %5, %2
mov %5, %3, 12
mov %6 // we prefer to omit the 2nd argument if it refers to the "zero
value register %0".
I know this is not difficult. I'm very much a beginner with LLVM: tablegen
and the instruction selection/code generation framework. I would welcome
some input on how best to approach all of this, i.e are there any notes
or documents describing the design of one of the backends currently
released? I have read the writing a backend information and am currently
modifying a copy of a SPARC backend to prototype.I have defined the
register set OK, and am working on defining the basic instructions. I'm not
sure where/how best to cope with the immediate value printing and immediate
value limiting to 17bits in instruction selection/code generation.
I had thought of using a multiclass definition for each instruction that
has an immediate present/omitted. Would I need to define a new 17bit type
Imm17 in CodeGen/ValueTypes.td/h, or can I cope with the 17 bit immediate
elsewhere by perhaps using an i32? OR, can I handle this elsewhere in
codegen/instruction selection more elegantly? Apologies for the naivety of
defm MOV : sabre_inst<"mov", 0b00000>;
defm ADD : sabre_inst<"add",0b00001>; // etc .... for other questions
Dr. Andy Nisbet: URL http://www.docm.mmu.ac.uk/STAFF/A.Nisbet Department of Computing and Mathematics, John Dalton Building, Manchester
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