How to select ISD::sdivrem node?

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How to select ISD::sdivrem node?

Pei-Shiang Hung-2
Hello all,

I'm a novice to porting a new LLVM backend.
My target has a native instruction named divrs which takes 2 input
operands  and produces 2 output results.

The format is
divrs $rt, $rs, $ra, $rb

The operation of divrs is
to divide $ra with $rb, then put quotient into $rt and remainder into $rs.

Therefore, I think I can map ISD::sdivrem to my native instruction
divrs directly.
I define the following pattern.

def DIVSR : F32_ALU1_DIV<(outs GPR5:$rt, GPR5:$rs), (ins GPR5:$ra,
GPR5:$rb), "divs", [(set i32:$rt, i32:$rs (sdivrem i32:$ra,

but, I get the following error message while running llvm-tblgen

llvm/llvm_3.6.1/llvm-3.6.1.src/include/llvm/ADT/SmallVector.h:138: T&
ctorTemplateCommon<T, <template-parameter-1-2>
<template-parameter-1-2> >::size_type) [with T = llvm::EEVT::TypeSet;
<template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <t
emplate-parameter-1-2> >::reference = llvm::EEVT::TypeSet&;
llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2>
>::size_type = long unsigned int]: Assertion `idx < size()' failed.
#0 0x7fc0285d5036 llvm::sys::PrintStackTrace(_IO_FILE*)
#1 0x7fc0285d52e0 PrintStackTraceSignalHandler(void*)
#2 0x7fc0285d3dd3 SignalHandler(int)
#3 0x7fc0275b2b80 (/lib64/
#4 0x7fc0275b2b07 gsignal
#5 0x7fc0275b3e9a abort
#6 0x7fc0275ab95d __assert_fail_base
#7 0x7fc0275aba12 (/lib64/
#8 0x49b52d llvm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet,
void>::operator[](unsigned long)
#9 0x485143 llvm::TreePatternNode::getExtType(unsigned int)
#10 0x496861 llvm::CodeGenDAGPatterns::parseInstructionPattern(llvm::CodeGenInstruction&,
llvm::ListInit*, std::map<ll
vm::Record*, llvm::DAGInstruction, llvm::LessRecordByID,
std::allocator<std::pair<llvm::Record* const, llvm::DAGInstru
ction> > >&) llvm/llvm_3.6.1/llvm-3.6.1.src/utils/TableGen/CodeGenDAGPatterns.cpp:2949:0
#11 0x496fe4 llvm::CodeGenDAGPatterns::ParseInstructions()

I'm not familiar of how llvm-tblgen generates patterns.
Can someone tell me what's wrong?

Thanks for the information.
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Re: How to select ISD::sdivrem node?

Matt Arsenault
On 07/08/2015 02:53 AM, Pei-Shiang Hung wrote:
> Therefore, I think I can map ISD::sdivrem to my native instruction
> divrs directly.
I don't think it is currently possible to write a pattern to match an
instruction that produces multiple outputs in tablegen. This requires
writing custom matching code in your ISelDAGToDAG.

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