Getting the target information of a branch instruction

Previous Topic Next Topic
 
classic Classic list List threaded Threaded
7 messages Options
Reply | Threaded
Open this post in threaded view
|

Getting the target information of a branch instruction

Abhinavkarhu
Hello all,
I am new to the llvm infrastructure so if this question is already
resolved please redirect me to that link.

I am writing a pass for flow sensitive and context sensitive alias
analysis.for that i require the previous and next instruction of all the
instructions.Is there an intrinsic that can help me getting the
instruction numbers directly because i read at the llvm.org website making
changes to instruction class may be lead to unstableness..Also if i have a
branch instruction how do i get he target of the branch instruction.All i
could find was machine independent target code.

Please enlighten me on this topic asap...
Thanks in advance..

Cheers,
Abhinav
_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Chris Lattner
On Mon, 2 Jul 2007 [hidden email] wrote:

> Hello all,
> I am new to the llvm infrastructure so if this question is already
> resolved please redirect me to that link.
>
> I am writing a pass for flow sensitive and context sensitive alias
> analysis.for that i require the previous and next instruction of all the
> instructions.Is there an intrinsic that can help me getting the
> instruction numbers directly because i read at the llvm.org website making
> changes to instruction class may be lead to unstableness..Also if i have a
> branch instruction how do i get he target of the branch instruction.All i
> could find was machine independent target code.

Is this in the code generator, or in the LLVM IR?   I assume that you mean
the LLVM IR.  Given an unconditional branch, you can use I->getOperand(0)
to get the destination.  You should check out this document, it describes
lots of interesting stuff:
http://llvm.org/docs/ProgrammersManual.html

in particular:
http://llvm.org/docs/ProgrammersManual.html#common

-Chris

--
http://nondot.org/sabre/
http://llvm.org/
_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Abhinavkarhu
> On Mon, 2 Jul 2007 [hidden email] wrote:
>> Hello all,
>> I am new to the llvm infrastructure so if this question is already
>> resolved please redirect me to that link.
>>
>> I am writing a pass for flow sensitive and context sensitive alias
>> analysis.for that i require the previous and next instruction of all the
>> instructions.Is there an intrinsic that can help me getting the
>> instruction numbers directly because i read at the llvm.org website
>> making
>> changes to instruction class may be lead to unstableness..Also if i have
>> a
>> branch instruction how do i get he target of the branch instruction.All
>> i
>> could find was machine independent target code.
>
> Is this in the code generator, or in the LLVM IR?   I assume that you mean
> the LLVM IR.  Given an unconditional branch, you can use I->getOperand(0)
> to get the destination.  You should check out this document, it describes
> lots of interesting stuff:
> http://llvm.org/docs/ProgrammersManual.html
>
> in particular:
> http://llvm.org/docs/ProgrammersManual.html#common
>
> -Chris
>
> --
> http://nondot.org/sabre/
> http://llvm.org/
> _______________________________________________
> LLVM Developers mailing list
> [hidden email]         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

Thanks a lot for the information.Actually i am looking for the target of
conditional branch operation something like

some instruction INST...
if(condition)
{
}
else
{
}..

In this case the next set for the instruction INST will consist of the
code in the true condition as well as the falses condition....
for that i am checking if the opcode is terminator and after that i am
getting the opcode name and if it is a branch instruction then i should
get the statement number of the branch...i am using a map to associate an
instruction with number...i had a look at the IR and it has inserted
cond_true,cond_false and cond_next labels in the IR of the bytecode...

How do i go further with these values in hand?
please guide on this topic.
Thanks a lot.
abhinav.
_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Seung Jae Lee
In reply to this post by Abhinavkarhu
I think you can refer to lib/VMCore/AsmWriter.cpp for these things.

E.g.,
You can use 'if(I.isTerminator())' if a instruction 'I' is terminator.
You can use 'if (isa<BranchInst>(I))' if a instruction 'I' is 'br' instruction.
and so on...

Thx,
Seung Jae Lee

---- Original message ----

>Date: Mon, 2 Jul 2007 17:15:00 -0400 (EDT)
>From: [hidden email]  
>Subject: Re: [LLVMdev] Getting the target information of a branch instruction  
>To: "LLVM Developers Mailing List" <[hidden email]>
>
>> On Mon, 2 Jul 2007 [hidden email] wrote:
>>> Hello all,
>>> I am new to the llvm infrastructure so if this question is already
>>> resolved please redirect me to that link.
>>>
>>> I am writing a pass for flow sensitive and context sensitive alias
>>> analysis.for that i require the previous and next instruction of all the
>>> instructions.Is there an intrinsic that can help me getting the
>>> instruction numbers directly because i read at the llvm.org website
>>> making
>>> changes to instruction class may be lead to unstableness..Also if i have
>>> a
>>> branch instruction how do i get he target of the branch instruction.All
>>> i
>>> could find was machine independent target code.
>>
>> Is this in the code generator, or in the LLVM IR?   I assume that you mean
>> the LLVM IR.  Given an unconditional branch, you can use I->getOperand(0)
>> to get the destination.  You should check out this document, it describes
>> lots of interesting stuff:
>> http://llvm.org/docs/ProgrammersManual.html
>>
>> in particular:
>> http://llvm.org/docs/ProgrammersManual.html#common
>>
>> -Chris
>>
>> --
>> http://nondot.org/sabre/
>> http://llvm.org/
>> _______________________________________________
>> LLVM Developers mailing list
>> [hidden email]         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>
>Thanks a lot for the information.Actually i am looking for the target of
>conditional branch operation something like
>
>some instruction INST...
>if(condition)
>{
>}
>else
>{
>}..
>
>In this case the next set for the instruction INST will consist of the
>code in the true condition as well as the falses condition....
>for that i am checking if the opcode is terminator and after that i am
>getting the opcode name and if it is a branch instruction then i should
>get the statement number of the branch...i am using a map to associate an
>instruction with number...i had a look at the IR and it has inserted
>cond_true,cond_false and cond_next labels in the IR of the bytecode...
>
>How do i go further with these values in hand?
>please guide on this topic.
>Thanks a lot.
>abhinav.
>_______________________________________________
>LLVM Developers mailing list
>[hidden email]         http://llvm.cs.uiuc.edu
>http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Tanya Lattner-2
In reply to this post by Abhinavkarhu

> Thanks a lot for the information.Actually i am looking for the target of
> conditional branch operation something like

The Programmers Manual that Chris suggested has this kind of information.
http://llvm.org/docs/ProgrammersManual.html#BasicBlock

If this is LLVM IR, get the Terminator instruction from the basic block.

Read up on TerminatorInst:
http://llvm.org/doxygen/classllvm_1_1TerminatorInst.html

For a conditional branch, you will get a BranchInst, check if its
conditional, and then you can get the successor blocks.

Does this answer your question?

-Tanya

>
> some instruction INST...
> if(condition)
> {
> }
> else
> {
> }..
>
> In this case the next set for the instruction INST will consist of the
> code in the true condition as well as the falses condition....
> for that i am checking if the opcode is terminator and after that i am
> getting the opcode name and if it is a branch instruction then i should
> get the statement number of the branch...i am using a map to associate an
> instruction with number...i had a look at the IR and it has inserted
> cond_true,cond_false and cond_next labels in the IR of the bytecode...
>
> How do i go further with these values in hand?
> please guide on this topic.
> Thanks a lot.
> abhinav.
> _______________________________________________
> LLVM Developers mailing list
> [hidden email]         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Abhinavkarhu
In reply to this post by Seung Jae Lee
Thanks a lot for the help guys..
I will try to get the information on these lines...

Thank you once again...
Will bug you guys after some time now.  :)

> I think you can refer to lib/VMCore/AsmWriter.cpp for these things.
>
> E.g.,
> You can use 'if(I.isTerminator())' if a instruction 'I' is terminator.
> You can use 'if (isa<BranchInst>(I))' if a instruction 'I' is 'br'
> instruction.
> and so on...
>
> Thx,
> Seung Jae Lee
>
> ---- Original message ----
>>Date: Mon, 2 Jul 2007 17:15:00 -0400 (EDT)
>>From: [hidden email]
>>Subject: Re: [LLVMdev] Getting the target information of a branch
>> instruction
>>To: "LLVM Developers Mailing List" <[hidden email]>
>>
>>> On Mon, 2 Jul 2007 [hidden email] wrote:
>>>> Hello all,
>>>> I am new to the llvm infrastructure so if this question is already
>>>> resolved please redirect me to that link.
>>>>
>>>> I am writing a pass for flow sensitive and context sensitive alias
>>>> analysis.for that i require the previous and next instruction of all
>>>> the
>>>> instructions.Is there an intrinsic that can help me getting the
>>>> instruction numbers directly because i read at the llvm.org website
>>>> making
>>>> changes to instruction class may be lead to unstableness..Also if i
>>>> have
>>>> a
>>>> branch instruction how do i get he target of the branch
>>>> instruction.All
>>>> i
>>>> could find was machine independent target code.
>>>
>>> Is this in the code generator, or in the LLVM IR?   I assume that you
>>> mean
>>> the LLVM IR.  Given an unconditional branch, you can use
>>> I->getOperand(0)
>>> to get the destination.  You should check out this document, it
>>> describes
>>> lots of interesting stuff:
>>> http://llvm.org/docs/ProgrammersManual.html
>>>
>>> in particular:
>>> http://llvm.org/docs/ProgrammersManual.html#common
>>>
>>> -Chris
>>>
>>> --
>>> http://nondot.org/sabre/
>>> http://llvm.org/
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> [hidden email]         http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>>
>>Thanks a lot for the information.Actually i am looking for the target of
>>conditional branch operation something like
>>
>>some instruction INST...
>>if(condition)
>>{
>>}
>>else
>>{
>>}..
>>
>>In this case the next set for the instruction INST will consist of the
>>code in the true condition as well as the falses condition....
>>for that i am checking if the opcode is terminator and after that i am
>>getting the opcode name and if it is a branch instruction then i should
>>get the statement number of the branch...i am using a map to associate an
>>instruction with number...i had a look at the IR and it has inserted
>>cond_true,cond_false and cond_next labels in the IR of the bytecode...
>>
>>How do i go further with these values in hand?
>>please guide on this topic.
>>Thanks a lot.
>>abhinav.
>>_______________________________________________
>>LLVM Developers mailing list
>>[hidden email]         http://llvm.cs.uiuc.edu
>>http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> _______________________________________________
> LLVM Developers mailing list
> [hidden email]         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Reply | Threaded
Open this post in threaded view
|

Re: Getting the target information of a branch instruction

Abhinavkarhu
Hello all,

The algorithm that i am trying to implement has this particular line that
says

if variable p gets a value at statement u
{
}

If i want to find out whether a particular variable gets a value at a
statement how can i do that.

Do i just need to check whether the getOperand(0) returns a non zero value
or is there any other way?

Please suggest something..
thankz in advance..






> Thanks a lot for the help guys..
> I will try to get the information on these lines...
>
> Thank you once again...
> Will bug you guys after some time now.  :)
>
>> I think you can refer to lib/VMCore/AsmWriter.cpp for these things.
>>
>> E.g.,
>> You can use 'if(I.isTerminator())' if a instruction 'I' is terminator.
>> You can use 'if (isa<BranchInst>(I))' if a instruction 'I' is 'br'
>> instruction.
>> and so on...
>>
>> Thx,
>> Seung Jae Lee
>>
>> ---- Original message ----
>>>Date: Mon, 2 Jul 2007 17:15:00 -0400 (EDT)
>>>From: [hidden email]
>>>Subject: Re: [LLVMdev] Getting the target information of a branch
>>> instruction
>>>To: "LLVM Developers Mailing List" <[hidden email]>
>>>
>>>> On Mon, 2 Jul 2007 [hidden email] wrote:
>>>>> Hello all,
>>>>> I am new to the llvm infrastructure so if this question is already
>>>>> resolved please redirect me to that link.
>>>>>
>>>>> I am writing a pass for flow sensitive and context sensitive alias
>>>>> analysis.for that i require the previous and next instruction of all
>>>>> the
>>>>> instructions.Is there an intrinsic that can help me getting the
>>>>> instruction numbers directly because i read at the llvm.org website
>>>>> making
>>>>> changes to instruction class may be lead to unstableness..Also if i
>>>>> have
>>>>> a
>>>>> branch instruction how do i get he target of the branch
>>>>> instruction.All
>>>>> i
>>>>> could find was machine independent target code.
>>>>
>>>> Is this in the code generator, or in the LLVM IR?   I assume that you
>>>> mean
>>>> the LLVM IR.  Given an unconditional branch, you can use
>>>> I->getOperand(0)
>>>> to get the destination.  You should check out this document, it
>>>> describes
>>>> lots of interesting stuff:
>>>> http://llvm.org/docs/ProgrammersManual.html
>>>>
>>>> in particular:
>>>> http://llvm.org/docs/ProgrammersManual.html#common
>>>>
>>>> -Chris
>>>>
>>>> --
>>>> http://nondot.org/sabre/
>>>> http://llvm.org/
>>>> _______________________________________________
>>>> LLVM Developers mailing list
>>>> [hidden email]         http://llvm.cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>>
>>>
>>>Thanks a lot for the information.Actually i am looking for the target of
>>>conditional branch operation something like
>>>
>>>some instruction INST...
>>>if(condition)
>>>{
>>>}
>>>else
>>>{
>>>}..
>>>
>>>In this case the next set for the instruction INST will consist of the
>>>code in the true condition as well as the falses condition....
>>>for that i am checking if the opcode is terminator and after that i am
>>>getting the opcode name and if it is a branch instruction then i should
>>>get the statement number of the branch...i am using a map to associate
>>> an
>>>instruction with number...i had a look at the IR and it has inserted
>>>cond_true,cond_false and cond_next labels in the IR of the bytecode...
>>>
>>>How do i go further with these values in hand?
>>>please guide on this topic.
>>>Thanks a lot.
>>>abhinav.
>>>_______________________________________________
>>>LLVM Developers mailing list
>>>[hidden email]         http://llvm.cs.uiuc.edu
>>>http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>> _______________________________________________
>> LLVM Developers mailing list
>> [hidden email]         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>
> _______________________________________________
> LLVM Developers mailing list
> [hidden email]         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

_______________________________________________
LLVM Developers mailing list
[hidden email]         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev